The present invention relates to a decoder circuit used in an integrated semiconductor circuit (IC) memory chip or die which comprises a memory cell matrix consisting of a plurality of memory cells. More particularly, the present invention relates to a decoder circuit adapted for a respective memory cell which requires two kinds of power supply voltages for programming and reading the data into and from the memory cell respectively. A specific example of this type of memory cell is an erasable programmable read only memory (EPROM) cell.
The memory cell matrix is composed of a plurality of word-lines and bit-lines, and an EPROM cell is placed at each intersection point of respective word-lines and bit-lines. The EPROM cell requires two kinds of power supply voltages--a high power supply voltage and a low power supply voltage--for programming and reading out the data into and from the cell respectively; the high and the low power supply voltages are supplied to the IC memory chip from its exterior. There is no difference among the decoder circuits, but there are two groups of the decoder circuits: the one group consists of row decoder circuits each provided for respective word-line, and the other group consists of column decoder circuits each provider for respective bit-lines. A designated EPROM cell transistor is selected by external address signals given from a computer system to which the IC memory chip belongs; the selection is done by applying row and column address signals to the row and the column decoder circuits respectively. For example, when the row address signals are applied to the row decoder circuits, one of the row decoder circuits outputs an H level. As a result, only one work-line is raised up to the H level so that the EPROM cell transistors, in which the gates are connected to the word-line, are ready to read out the data. The same process is also enforced to the bit-line through the column decoder circuit, so that a designated EPROM cell transistor can be selected so as to be ready to read out the data. In this case, it is said that the row and column decoder circuits are in a selective state and other decoder circuits are in a non-selective state hereinafter.
Thus, the total number of the decoder circuits fabricated in the IC memory chip are as many as the total number of the word-lines and the bit-lines. The row decoder circuit and the column decoder circuit are similar to each other, so the row decoder circuit will be discussed below.
FIG. 2 is a conventional row decoder circuit of the prior art, and it shows a case in which the row decoder circuit receives a unique combination of address signals composed of 3 bits, a.sub.0 /a.sub.0 .about.a.sub.2 /a.sub.2 :a.sub.i /a.sub.i means a.sub.i or a.sub.i, and a.sub.i means an inverted signal of a.sub.i such that when a.sub.i is a signal having a high level, a.sub.i is a signal having a low level. These internal address signals are generated inside the semiconductor chip in response to the external address signals applied to the chip from the exterior. So, the row decoder circuit of FIG. 2 is one of eight row decoder circuits, and a word-line WL is one of eight word-lines.
In FIG. 2, all MOS transistors used in the circuit are enhancement (E) type, and Q.sub.n1 .about.Q.sub.n5 are n channel MOS transistors and Q.sub.p1 .about.Q.sub.p3 are p channel MOS transistors. Two kinds of voltage sources--V.sub.cc and V.sub.ppi --are applied to the circuit: V.sub.cc is a fixed low power supply voltage (5 volts (V) for example) and V.sub.ppi is a variable power supply voltage. The variable power supply voltage V.sub.ppi is changed so as to be a high power supply voltage V.sub.pp (12.5 V or 21 V for example) when a datum is programmed into an EPROM, and the low power supply voltage V.sub.cc when a datum is read out from an EPROM. Symbol V.sub.ss means the earth potential.
Transistors Q.sub.n1 .about.Q.sub.n3 and Q.sub.p1 compose a NAND gate and receive 3 address inputs at the same time. The output level of the NAND gate at output node X becomes low (L) when all of the 3 address inputs are in a high (H) level; and the decoder circuit is in the selective state. The output level at output node X becomes H when at least one of the 3 address inputs is in the L level; and the decoder circuit is in the non-selective state. The output of the NAND gate at node X is fed to the gates of transistors Q.sub.p3 and Q.sub.n5, which compose a CMOS inverter, through a transfer gate Q.sub.n4. The CMOS inverter operates as follows: when the output level of the NAND gate at node X become L, transistors Q.sub.n5 and Q.sub.p3 turn OFF and ON respectively so that an H level (equal to the level of V.sub.ppi) is outputted to word-line WL, and when the level at node X become H, transistors Q.sub.n5 and Q.sub.p3 turn ON and OFF respectively so that an L level is outputted to word-line WL. Thus, when the row decoder circuit is in the selective state, the level on word-line WL becomes H so that an EPROM cell transistor having its gate connected to the word-line, becomes able to read out the datum or program the datum.
Transistor Q.sub.p2 is a pull-up transistor used as a level compensator. When the IC memory chip is in a programming mode which is a mode to program a datum into the EPROM, variable power supply voltage V.sub.ppi is switched to high power supply voltage V.sub.pp. However, when the level at node X of the NAND gate is H and if there were no transistor Q.sub.p2 in the decoder circuit, an input signal (level) of inverter Q.sub.p3 -Q.sub.n5 could not reach an voltage level higher than power supply voltage V.sub.cc. This is due to a fact that the NAND gate always uses low power supply voltage V.sub.cc as the power supply voltage. If so, the inverter Q.sub.p3 -Q.sub.n5 would become unstable; the inverter could not produce a stable L level. In addition, a large DC current would flow constantly through transistors Q.sub.p3 and Q.sub.n5 from the power supply to the earth since both the transistors would be ON under this condition, resulting in large power consumption. This can be compensated by transistor Q.sub.p2 ; when the level on the word-line WL becomes L, the level L is fed back to transistor Q.sub.p2 turning it ON, so high power supply voltage V.sub.pp is applied to the gates of the inverter Q.sub.p3 -Q.sub.n5 so that transistor Q.sub.p3 completely cuts off; then the level on the word-line WL can be fixed to L so that word-line WL completely becomes a non-selected state.
At this moment, the level at node X and the level at the gates of the inverter Q.sub.p3 -Q.sub.n5 become almost equal to low power supply voltage V.sub.cc and high power supply voltage V.sub.pp respectively. The transfer gate of transistor Q.sub.n4 is to prevent the competition of the V.sub.cc and V.sub.pp ; when transistor Q.sub.p2 pulls up the voltage on the gates of the inverter Q.sub.p3 -Q.sub.n5 to high power supply voltage V.sub.pp, transistor Q.sub.n4 is driven to be cut off.
When the level at node X is L in the programming mode, which means that the decoder circuit is in the selective state, the level appearing on word-line WL becomes H, so transistor Q.sub.p3 turns OFF; then transistor Q.sub.p3 of the inverter turns ON so that the level on word-line WL completely becomes H as high as power supply voltage V.sub.pp.
When the row decoder circuit is in a reading mode which is a mode to read out data stored in the EPROM, variable power supply voltage V.sub.ppi switches to low power supply voltage V.sub.cc and the compensator and the transfer gate functions similarly to the above in the programming mode.
As explained above, the transistors of the compensator and the transfer gate are necessary for maintaining each level of the word-line and the bit-line so as to avoid a large constant current at the CMOS inverter and obtain a stable low level output in respective rows and columns of the decoder circuit. Thus, there are many IC elements like transistors and wirings in each decoder circuit, and as many decoder circuits are required as the number of the row and bit lines in the IC memory chip. So, even though the memory matrix consisting of the EPROMs can be integrated in a high packing density within the skill of the art, the area for the decoder circuits becomes dominant in a space factor and increases difficulty of fabricating a small IC memory chip. Especially, the area becomes a big problem for compactly designing a high density IC memory chip having memory capacity such as 256 kilo-bits (K-bits) or more.